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W9812G6GH 2M X 4 BANKS X 16 BITS SDRAM
Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION .............................................................................................................. 3 FEATURES...................................................................................................................................... 3 AVAILABLE PART NUMBER .......................................................................................................... 3 PIN CONFIGURATION.................................................................................................................... 4 PIN DESCRIPTION ......................................................................................................................... 5 BLOCK DIAGRAM........................................................................................................................... 6 FUNCTIONAL DESCRIPTION ........................................................................................................ 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 8. 9. Power Up and Initialization ................................................................................................. 7 Programming Mode Register .............................................................................................. 7 Bank Activate Command .................................................................................................... 7 Read and Write Access Modes .......................................................................................... 7 Burst Read Command ........................................................................................................ 8 Burst Write Command......................................................................................................... 8 Read Interrupted by a Read ............................................................................................... 8 Read Interrupted by a Write................................................................................................ 8 Write Interrupted by a Write ................................................................................................ 8 Write Interrupted by a Read................................................................................................ 8 Burst Stop Command.......................................................................................................... 9 Addressing Sequence of Sequential Mode......................................................................... 9 Addressing Sequence of Interleave Mode.......................................................................... 9 Auto-precharge Command................................................................................................ 10 Precharge Command........................................................................................................ 10 Self Refresh Command..................................................................................................... 10 Power Down Mode............................................................................................................ 11 No Operation Command ................................................................................................... 11 Deselect Command .......................................................................................................... 11 Clock Suspend Mode........................................................................................................ 11
OPERATION MODE...................................................................................................................... 12 ELECTRICAL CHARACTERISTICS ............................................................................................. 13 9.1 9.2 9.3 Absolute Maximum Ratings .............................................................................................. 13 Recommended DC Operating Conditions ........................................................................ 13 Capacitance ...................................................................................................................... 13 Publication Release Date:Aug. 13, 2007 Revision A06
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W9812G6GH
9.4 9.5 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 12.1 DC Characteristics ............................................................................................................ 14 AC Characteristics and Operating Condition .................................................................... 15 Command Input Timing..................................................................................................... 17 Read Timing...................................................................................................................... 18 Control Timing of Input/Output Data ................................................................................. 19 Mode Register Set Cycle .................................................................................................. 20 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 21 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............... 22 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 23 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............... 24 Interleaved Bank Write (Burst Length = 8) ....................................................................... 25 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26 Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................... 27 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 29 Auto Precharge Write (Burst Length = 4) ......................................................................... 30 Auto Refresh Cycle ........................................................................................................... 31 Self Refresh Cycle ............................................................................................................ 32 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33 Power Down Mode............................................................................................................ 34 Auto-precharge Timing (Read Cycle) ............................................................................... 35 Auto-precharge Timing (Write Cycle) ............................................................................... 36 Timing Chart of Read to Write Cycle ................................................................................ 37 Timing Chart of Write to Read Cycle ................................................................................ 37 Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38 Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 38 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40 54L TSOP (II)-400 mil ....................................................................................................... 41
10. TIMING WAVEFORMS.................................................................................................................. 17
11. OPERATING TIMING EXAMPLE.................................................................................................. 21
12. PACKAGE SPECIFICATION......................................................................................................... 41 13. REVISION HISTORY..................................................................................................................... 42
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1. GENERAL DESCRIPTION
W9812G6GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words x 4 banks x 16 bits. Using pipelined architecture and 0.11 m process technology, W9812G6GH delivers a data bandwidth of up to 166M words per second (-6). For different application, W9812G6GH is sorted into two speed grades: -6/6C/6I, -75. The -6/6C/6I is compliant to the 166Mhz/CL3 specification, the -75 is compliant to the 133MHz/CL3 specification. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G6GH is ideal for main memory in high performance applications.
2. FEATURES
* * * * * * * * * * * * * * 3.3V 0.3V Power Supply Up to 166 MHz Clock Frequency 2,097,152 Words x 4 banks x 16 bits organization Self Refresh Mode CAS Latency: 2and 3 Burst Length: 1, 2, 4, 8 and full page Burst Read, Single Writes Mode Byte Data Controlled by DQM Auto-precharge and Controlled Precharge 4K Refresh cycles / 64 mS Interface: LVTTL Packaged in TSOP II 54 pin, 400 mil - 0.80 W9812G6GH is using Lead free materials RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER SPEED MAXIMUM SELF REFRESH CURRENT OPERATING TEMPERATURE
W9812G6GH-6 W9812G6GH-6C W9812G6GH-6I W9812G6GH-75
166MHz/CL3 166MHz/CL3 166MHz/CL3 133MHz/CL3
2 mA 2 mA 2 mA 2 mA
0C ~ 70C 0C ~ 70C -40C ~ 85C 0C ~ 70C
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4. PIN CONFIGURATION
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 V CC Q DQ12 DQ11 VSS Q DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
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5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION DESCRIPTION
23 - 26, 22, 29 - 35 20, 21 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 19
A0 - A11 BS0, BS1 DQ0 - DQ15
Address Bank Select Data Input/ Output
Multiplexed pins for row and column address. Row address: A0 - A11. Column address: A0 - A8. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed.
CS
Chip Select Row Address Strobe
18 17 16 39, 15
RAS CAS
WE
Column Address Referred to RAS Strobe Write Enable Input/Output Mask Clock Inputs Clock Enable Power (+3.3V) Ground Power (+3.3V) for I/O Buffer Ground for I/O Buffer No Connection Referred to RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection
UDQM/ LDQM CLK CKE VCC VSS VCCQ VSSQ NC
38 37 1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40
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6. BLOCK DIAGRAM
CLK C LO CK BU FFER
C KE
CS
R AS C AS
CONTROL SIGNAL GENERATOR
CO M MA ND DEC ODE R C OLUM N D ECO DER
WE
C OLUM N D ECO DER R O W
R O W D E C O D E R
A10
CELL ARRAY BANK #0
A0 AD DRES S BU FFER A9 A11 BS0 BS1
M O DE REG ISTER
D E C O D E R
CELL ARRAY BANK #1
SENSE A MPLIFIER
SENSE A MPLIFIER
DM n
DQ0
DATA CONTRO L CIRCUIT
RE FRESH CO UNTE R C OLUM N C OUN TER
DQ BUFFER
DQ15 UDQM LDQM
CO LUM N DE COD ER R O W D E C O D E R R O W
COLU MN D ECO DER
CELL ARRAY BANK #2
D E C O D E R
CELL ARRAY BANK #3
SEN SE AM PLIFIER
SEN SE AM PLIFIE R
Note: The cell array configuration is 4096 * 512 * 16.
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7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.
7.2
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS (max).
7.4
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. Publication Release Date:Aug. 13, 2007 -Revision A06
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7.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.
7.6
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.
7.7
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied.
7.8
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.
7.9
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.
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7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2 BL = 4 BL = 8
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7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is entered. During Auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with Auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The period between the Auto Refresh command and the next command is specified by tRC.
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7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.
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8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2))
COMMAND
Bank Active Bank Precharge Precharge All Write Write with Auto-precharge Read Read with Auto-precharge Mode Register Set No - Operation Burst Stop Device Deselect Auto - Refresh Self - Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit
DEVICE STATE
Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R.) Active Idle Active (5) Active Any (power down) Active Active
CKEn-1 CKEn DQM BS0, 1 A10
H H H H H H H H H H H H H L L H H H L L L H H x x x x x x x x x x x H L H H L L L H H H x x x x x x x x x x x x x x x x x x x x x x x L H v v x v v v v v x x x x x x x x x x x x x x x v L H L H L H v x x x x x x x x x x x x x x x
A0-A9 A11
v x x v v v v v x x x x x x x x x x x x x x x
CS RAS
L L L L L L L L L L H L L H L x H L x H L x x L L L H H H H L H H x L L x H x x H x x H x x
CAS
H H H L L L L L H H x L L x H x x H x x H x x
WE
H L L L L H H L H L x H H x x x x x x x x x x
Power Down Mode Exit
Data write/Output Enable Data Write/Output Disable Notes: (1) v = valid x = Don't care
L = Low Level
H = High Level
(2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode.
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9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER SYMBOL RATING UNIT
Input/Output Voltage Power Supply Voltage Operating Temperature(-6/6C/-75) Operating Temperature(-6I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current
VIN, VOUT VCC, VCCQ TOPR TOPR TSTG TSOLDER PD IOUT
-0.3 ~ VCC + 0.3 -0.3 ~ 4.6 0 ~ 70 -40 ~ 85 -55 ~ 150 260 1 50
V V C C C C W mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9.2
Recommended DC Operating Conditions
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
(Ta = 0 to 70C for -6/-6C/-75 , Ta= -40 to 85C for -6I )
Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage
VCC VCCQ VIH VIL
3.0 3.0 2.0 -0.3
3.3 3.3 -
3.6 3.6 VCC + 0.3 0.8
V V V V
Note: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS
9.3
Capacitance
PARAMETER SYMBOL MIN. MAX. UNIT
(VCC = 3.3V, f = 1 MHz, Ta 25C)
Input Capacitance (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) Input Capacitance (CLK) Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
CI CCLK CIO
-
3.8 3.5 6.5
pf pf pf
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9.4 DC Characteristics
(VCC = 3.3V 0.3V, Ta = 0 to 70C for -6/-6C/-75, Ta= -40 to 85C for -6I)
PARAMETER
Operating Current
SYM.
-6/-6C/-6I MAX.
-75 MAX.
UNIT
NOTES
tCK = min., tRC = min.
Active precharge command cycling without burst operation Standby Current
1 bank operation
ICC1
100
85
3
tCK = min,
CS = VIH
CKE = VIH CKE = VIL (Power
Down mode)
ICC2
30
30
3
VIH/L = VIH(min)/VIL(max.) Bank: Inactive state Standby Current CLK = VIL, CS = VIH VIH/L = VIH(min)/VIL(max) BANK: Inactive state No Operating Current
ICC2P
2
2
3
CKE = VIH CKE = VIL (Power
down mode)
ICC2S
15
15
ICC2PS ICC3 ICC3P
2 65 15
2 mA 60 15
tCK = min., CS = VIH(min)
BANK: Active state (4 banks) Burst Operating Current
CKE = VIH CKE = VIL (Power
down mode)
tCK = min.
Read/ Write command cycling Auto Refresh Current
ICC4
120
100
3, 4
tCK = min.
Auto refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2V
ICC5
200
190
3
ICC6
2
2
PARAMETER
Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V VOUT VCCQ) LVTTL Output H Level Voltage (IOUT = -2 Ma ) LVTTL Output L Level Voltage (IOUT = 2 Ma )
SYMBOL
II(L) IO(L) VOH VOL
MIN.
-5 -5 2.4 -
MAX.
5 5 0.4
UNIT
A A V V
NOTES
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9.5 AC Characteristics and Operating Condition
-6/-6I MIN. MAX. MIN. 6C MAX. -75 MIN. MAX.
(Vcc = 3.3V 0.3V, Ta = 0 to 70C for -6/-6C/-75, Ta= -40 to 85C for -6I, Notes: 5,6,7,8,9,10)
PARAMETER SYM. UNIT NOTES
Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time CLK Cycle Time CL* = 2 CL* = 3 CL* = 2 CL* = 3
tRC tRAS tRCD tCCD tRP tRRD tWR tCK tCH tCL
60 42 18 1 18 12 2 2 10 6 1000 100000
60
65 nS
42 100000 45 100000 18 1 18 12 20 1 20 15 2 2 10 7.5 1000
tCK
nS tCK
-2
-6
CLK High Level width CLK Low Level width
Access Time from CLK Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time Exit self refresh to ACTIVE command
*CL = CAS Latency * -- = not support
2 2
6 5 3 3 0 0 0.5 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 64 12 72 6 1 6
2 2
-5 3 3 0 0 0.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 64 12 72 6 1 6
2.5 2.5
6 5.4 3 3 0 0 0.5 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 64 15 75 mS nS nS 7.5 1 7.5 nS
9 9
CL* = 2 CL* = 3
tAC tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC tXSR
10 10 8 10
7 9 9 9 9 9 9 9 9
- 15
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
Notes: 1. Operation exceeds "Absolute Maximum Ratings" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence is further described in the "Functional Description" section. 6. AC Testing Conditions
PARAMETER CONDITIONS
Output Reference Level Output Load Input Signal Levels (VIH/VIL) Transition Time (tT: tr/tf) of Input Signal Input Reference Level
1.4V See diagram below 2.4V/0.4V 1/1 nS 1.4V
1.4 V
50 ohms
output
Z = 50 ohms 30pF
AC TEST LOAD
7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 9. Assumed input rise and fall time (tT ) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter ( The tT maximum can't be more than 10nS for low frequency application. ) 10. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
- 16 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCL
tCH
CLK
VIH VIL
tCMS tCMH tT tCMH tT tCMS
CS
tCMS
tCMH
RAS
tCMS
tCMH
CAS
tCMS
tCMH
WE
tAS
tAH
A0-A11 BS0, 1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
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Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11 BS0, 1
tAC tLZ tOH
Valid Data-Out
tAC
tHZ tOH
Valid Data-Out
DQ
Read Command
Burst Length
- 18 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMH tCMS tCMH tCMS
DQM
tDS tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -15
(Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tDS tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -15
Control Timing of Output Data
(Output Enable)
CLK
tCMH tCMS tCMH tCMS
DQM
tAC tOH tOH tAC tHZ tOH
Valid Data-Out
tLZ
tAC tOH
Valid Data-Out
tAC
DQ0 -15
Valid Data-Out
OPEN
(Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tAC tOH tAC tOH
Valid Data-Out Valid Data-Out
tAC tOH tOH
Valid Data-Out
tAC
DQ0 -15
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Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
10.4 Mode Register Set Cycle
tRSC
CLK
tCMS
tCMH
CS
tCMS
tCMH
RAS
tCMS
tCMH
CAS
tCMS
tCMH
WE
tAS
tAH
Register set data
A0-A11 BS0,1
A0
A1
A2
A3
A4
A5
A6
A0 A7
"0"
"0"
Burst Length
Addressing Mode
CAS Latency
A2 0 0 0 0 1 1 1 1
A0 A0 A1 A0 A0 0 0 A0 1 0 A0 0 1 A0 1 1 A0 0 0 A0 1 0 A0 0 1 A0 1 1
next command BurstA0 Length A0 Sequential A0 Interleave 1 A0 1 A0 A0 2 2 A0 4 A0 4 A0 8 A0 8
A0 Reserved
FullA0 Page
A0 Reserved
(Test Mode)
Reserved
A0 Write Mode
A6 0 0 0 0 1
A0 A3 A0 0 A0 1
A0 A5 A4 A0 0 0 A0 1 0 A0 0 1 A0 1 1 A0 0 0
A0 Addressing Mode A0 Sequential A0 Interleave
A0 CAS Latency A0 Reserved A0 Reserved 2 A0 3 Reserved
A8
A0 A9
A10
A0 A11
BS0
BS1
"0"
"0" "0"
A0 Reserved
"0"
A0 A9 A0 0 A0 1
Single Write Mode A0 Burst read and Burst write A0 Burst read and single write
- 20 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC tRC tRC tRC tRAS tRP tRP tRAS
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
RBd
tRCD
RAe
A10 A0-A9, A11 DQM
RAa
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
CKE
tAC tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Active
Precharge Read
Active
Read Precharge Active
Precharge Read
Active
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Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC tRC tRC tRC tRAS tRP tRP tRAS
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
tRCD
RBd RAe
A10
RAa
A0-A9, A11 DQM CKE
RAa
CAw RBb
CBx
RAc
CAy
RBd
CBz
RAe
tAC
tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
dz0
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3 Idle
Active
Read Active
AP* Read
Active
Read AP* Active
AP* Read
Active
* AP is the internal precharge start timing
- 22 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC tRC tRC
RAS
tRAS tRP tRP tRAS tRAS tRP
CAS WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
A10
RAa
A0-A9, A11 DQM
RAa
CAx
RBb
CBy
RAc
CAz
CKE
tAC tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6
tAC
by7 CZ0
DQ
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read Precharge Active Read
Precharge
Active
Read Precharge
Idle
- 23
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
0
1
2
3
4
5
6
7
8
tRC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
RAS
tRAS tRP tRAS tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
A10
RAa
A0-A9, A11 DQM
RAa
CAx
RBb
CBy
RAc
CAz
CKE
tCAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7
tCAC
by0 by1 by4 by5
tCAC
by6 CZ0
DQ
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read Active
AP* Read
Active
Read AP*
Idle
* AP is the internal precharge start timing
- 24 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.5 Interleaved Bank Write (Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC
RAS
tRAS tRP tRAS tRAS tRP
CAS
tRCD tRCD tRCD
WE
BS0 BS1
A10
RAa
RBb
RAc
A0-A9, A11 DQM
RAa
CAx
RBb
CBy
RAc
CAz
CKE DQ
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3
Active
Write Active Write
Precharge
Active
Write Precharge
Idle
- 25
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC
RAS
tRAS tRP tRAS
CAS
WE
BS0 BS1
tRCD
tRCD
RBb RAb
tRCD
A10
RAa
A0-A9 A11 DQM CKE DQ
RAa
CAx
RBb
CBy
RAc
CAz
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Bank #3 Idle
Write Active Write
AP*
Active
Write AP*
* AP is the internal precharge start timing
- 26 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tCCD tCCD tCCD
CS
tRAS tRAS tRP tRP
RAS
CAS
WE BS0
BS1
tRCD tRCD
RBb
A10 A0-A9, A11 DQM CKE
RAa
RAa
CAI
RBb
CBx
CAy
CAm
CBz
tAC
tAC
a0 a1 a2 a3 bx0 bx1
tAC
tAC
tAC
am0 am1 am2 bz0 bz1 bz2 bz3
DQ
tRRD
Ay0
Ay1
Ay2
Bank #0 Active Bank #1 Bank #2 Bank #3 Idle
Read Active Read
Read
Read Read
Precharge AP*
* AP is the internal precharge start timing
- 27
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS RAS CAS
tRAS
tRP
WE
BS0 BS1
tRCD
A10
RAa
A0-A9, A11
RAa
CAx
CAy
DQM CKE
tAC tWR
ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4
DQ
QQ
Q
Q
Q
Q
D
D
D
D
D
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read
Write
Precharge
Idle
- 28 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
CLK CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
tRC
tRC
RAS
tRAS tRP tRAS tRP
CAS
WE BS0
BS1
tRCD tRCD
RAb
A10
RAa
A0-A9, A11 DQM CKE
RAa
CAw
RAb
CAx
tAC
tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
DQ
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read
AP*
Active
Read
AP*
Idle * AP is the internal precharge start timing
- 29
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.10 Auto Precharge Write (Burst Length = 4)
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CS
tRC tRC
RAS
tRAS tRP tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD
RAb RAc
A10 A0-A9, A11 DQM CKE DQ
RAa
RAa
CAw
RAb
CAx
RAc
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
Bank #0 Bank #1 Bank #2 Bank #3
Active
Write
AP*
Active
Write
AP*
Active
Idle * AP is the internal precharge start timing
- 30 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.11 Auto Refresh Cycle
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tRP tRC tRC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9, A11
DQM
CKE DQ
All Banks Prechage
Auto Refresh
Auto Refresh (Arbitrary Cycle)
- 31
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.12 Self Refresh Cycle
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS CAS
WE
BS0,1
A10
A0-A9, A11
DQM
tSB
tCKS
tCKS
CKE
tCKS
DQ
tXSR
Self Refresh Cycle All Banks Precharge Self Refresh Exit
No Operation / Command Inhibit
Self Refresh Entry
Arbitrary Cycle
- 32 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS RAS
CAS
tRCD
WE BS0
BS1
A10
RBa
A0-A9, A11 DQM CKE
RBa
CBv
CBw
CBx
CBy
CBz
tAC
tAC
av0 Q av1 Q av2 Q av3 Q aw0 D ax0 D ay0 D az0 Q az1 Q az2 Q az3 Q
DQ
Bank #0 Active Bank #1 Bank #2 Bank #3 Idle
Read
Single Write
Read
- 33
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.14 Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
RAa
A0-A9 A11 DQM
RAa
CAa
RAa
CAx
tSB
tSB
CKE
tCKS tCKS
ax0 ax1 ax2
tCKS
ax3
tCKS
DQ
Active
NOP Read
Precharge
NOP Active Precharge Standby Power Down mode
Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data.
- 34 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.15 Auto-precharge Timing (Read Cycle)
0
(1) CAS Latency=2
( a ) burst length = 1 Command
1 AP
2
3 Act
4
5
6
7
8
9
10
11
Read
tRP
DQ
( b ) burst length = 2 Command
Q0 Read AP Q0 Read Q0 Read Q0 Read AP Q1 Q2 Act Q0 Read AP Q0 Read Q0 Read Q0 Q1 Q2 Q3 Q4
tRP tRP
Act
DQ
( c ) burst length = 4 Command
Q1 AP Q1 Q2
tRP
Act
DQ
( d ) burst length = 8 Command
Q3 AP Q3 Q4 Q5 Q6 Q7
tRP
Act
DQ (2) CAS Latency=3
( a ) burst length = 1 Command
tRP
DQ
( b ) burst length = 2 Command
Act Q1 AP Q1 Q2
tRP
DQ
( c ) burst length = 4 Command
Act Q3 AP Q5 Q6
tRP
DQ
( d ) burst length = 8 Command
Act Q7
DQ
Note )
Read AP Act
represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min).
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Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.16 Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
tWR
AP
tRP
Act
DQ
(b) burst length = 2
Command
D0
Write
tWR
AP
tRP
Act
DQ
(c) burst length = 4
Command
D0
Write
D1
AP
tWR
Act
tRP
DQ
(d) burst length = 8
Command
D0
Write
D1
D2
D3
AP
tWR
Act
tRP
DQ
(2) CAS Latency = 3
(a) burst length = 1 Command
D0
D1
D2
D3
D4
D5
D6
D7
Write
tWR
AP
tRP
Act
DQ
(b) burst length = 2 Command
D0
Write
tWR
AP
tRP
Act
DQ
(c) burst length = 4
Command
D0
Write
D1
AP
tWR
Act
tRP
DQ
(d) burst length = 8
Command
D0
Write
D1
D2
D3
AP
tWR
Act Act
tRP
DQ
D0
D1
D2
D3
D4
D5
D6
D7
Note )
Write
AP Act
represents the Write with Auto precharge command. represents the start of internal precharing. represents the Bank Active command.
When the /auto precharge command is asserted,the period from Bank Activate command to the start of intermal precgarging must be at least tRAS (min).
- 36 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
(1) CAS Latency=2
( a ) Command DQM DQ
0
1
2
3
4
5
6
7
8
9
10
11
Read Write
D0 Read
D1 Write D0
D2
D3
( b ) Command
DQM
DQ
D1
D2
D3
(2) CAS Latency=3
( a ) Command DQM
Read Write D0 Read D1 Write D0 D1 D2 D3 D2 D3
DQ ( b ) Command DQM
DQ
Note: The Output data must be masked by DQM to avoid I/O conflict
11.18 Timing Chart of Write to Read Cycle
In the case of Burst Length=4
0
(1) CAS Latency=2
( a ) Command DQM DQ ( b ) Command DQM DQ
1
2
3
4
5
6
7
8
9
10
11
Write Read D0 Write D0 D1 Read Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
(2) CAS Latency=3
( a ) Command DQM DQ ( b ) Command DQM DQ
Write Read D0 Write D0 D1 Read Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
- 37
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
(1) Read cycle ( a ) CAS latency =2
Command
1
2
3
4
5 BST
6
7
8
9
10
11
Read
Q0
Read
Q0
Q1
DQ
Q1
Q2
Q3
BST
Q2
Q4
( b )CAS latency = 3
Command
DQ
Q3
Q4
(2) Write cycle
Command
Write
BST
DQ
Q0
Q1
Q2
Q3
Q4
Note:
BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
(1) Read cycle (a) CAS latency =2
Command
1
2
3
4
5
6
7
8
9
10
11
Read
Q0
PRCG
Q1
DQ
Q2
Q3
Q4
(b) CAS latency =3
Command
Read
Q0
PRCG
Q1
DQ
Q2
Q3
Q4
(2) Write cycle (a) CAS latency =2
Command
Write
tWR
PRCG
DQM
DQ
Q0
Q1
Q2
Q3
Q4
(b) CAS latency =3
Command
Write
PRCG
tWR
DQM
DQ
Q0
Q1
Q2
Q3
Q4
- 38 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
11.21 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
3
4
5
6
7
External
CLK
Internal CKE DQM DQ
D1
D2
D3
DQM MASK
(1)
D5
CKE MASK
D6
CLK cycle No.
1
2
3
4
5
6
7
External
CLK
Internal CKE DQM DQ
D1
D2
D3
DQM MASK
(2)
D5
CKE MASK
D6
CLK cycle No. External
1
2
3
4
5
6
7
CLK
Internal
CKE DQM DQ
D1
D2
D3
CKE MASK
(3)
D4
D5
D6
- 39
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
11.22 CKE/DQM Input Timing (Read Cycle)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Open Open
Q6
(1)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Open
Q6
(2)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Q5
Q6
(3)
- 40 -
Publication Release Date:Aug. 13, 2007 Revision A06
W9812G6GH
12. PACKAGE SPECIFICATION
12.1 54L TSOP (II)-400 mil
54
28
E
HE
1 e D b
27
C
L A2 ZD A A1 SEATING PLANE L1
Y
Controlling Dimension: Millimeters
DIMENSION (MM) MIN.
0.05 0.24 22.12 10.06 11.56 0.40
SYM.
DIMENSION (INCH) MAX.
1.20 0.15 0.40 22.62 10.26 11.96 0.60 0.10
NOM.
0.10 1.00 0.32 0.15 22.22 10.16 11.76 0.80 0.50 0.80 0.71
MIN.
0.002 0.009 0.871 0.396 0.455 0.016
NOM.
0.004 0.039 0.012 0.006 0.875 0.400 0.463 0.0315 0.020 0.032
MAX.
0.047 0.006 0.016 0.905 0.404 0.471 0.024 0.004
A
A1 A2 b c D E HE e L L1 Y ZD
0.028
- 41
Publication Release Date:Aug. 13, 2007 -Revision A06
W9812G6GH
13. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A01 A02 A03 A04 A05 A06
Mar. 24, 2006 Sep. 08, 2006 Mar. 27, 2006 Feb. 07, 2007 Apr. 09, 2007 Aug. 13, 2007
All 10 15,16
Create new datasheet Exit Auto refresh to next command is specified by tRC Modify Characteristics Notes 9 and add Notes 10 (tT)
3,13,14,15 Add -6C grade for tIHmin=0.8nS 15,32,34 Add tXSR timing specification
3,13,14,15 Add -6I grade for Ta= -40 to 85C 16 Revise transient time tT AC test condition and calculate formula for compensation consideration in Notes 6, 9 of AC Characteristics and Operating Condition
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 42 -
Publication Release Date:Aug. 13, 2007 Revision A06

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